In present semiconductor technology, complementary metal oxide semiconductor (CMOS) devices, such as n-type field effect transistors (FETs) or NFETs, are typically fabricated on semiconductor wafers, such as silicon wafers that have a single crystal orientation, sometimes also referred to as direction. In particular, most of today's semiconductor devices are built on silicon substrates having a (100) crystal orientation.
Electrons are known to have high mobility for a (100) Si crystal orientation, but holes are known to have high mobility for a (110) crystal orientation. Typically, hole mobility values on (100) Si are roughly two times to about four times lower than the corresponding electron mobility for the same crystal orientation. To compensate for this discrepancy, PFETs are typically designed with greater widths in order to balance pull-up currents against the NFET pull-down currents and achieve uniform circuit switching. PFETs having greater widths are undesirable since they occupy a relatively greater amount of chip area. On the other hand, hole mobilities on (110) Si are about two times higher than on (100) Si. Therefore, PFETs formed on a (110) surface will exhibit significantly higher drive currents than PFETs formed on a (100) surface. Unfortunately, electron mobilities on (110) Si surfaces are significantly degraded compared to (100) Si surfaces.
As can be deduced from the above, the (110) Si surface is optimal for PFET devices because of excellent hole mobility, yet such a crystal orientation is inappropriate for NFET devices. Instead, the (100) Si surface is optimal for NFETs.
In view of the above, methods for fabricating integrated semiconductor devices upon a substrate having different crystal orientations have been explored. FIGS. 1 through 4 illustrate cross-sectional views of intermediate stages of a prior art method. The initial substrate includes a substrate 10 having an SOI structure, which includes an insulating layer 14 on a first semiconductor layer 12, and a second semiconductor layer 16 on the insulating layer 14. Preferably, one of the first and the second semiconductor layers is in a (100) direction and the other is in a (110) direction. The substrate 10 includes two regions 22 and 24. A dielectric layer (pad layer) 18 and a mask layer 20 are formed on the substrate 10. Layers 14, 16, 18 and 20 are then removed from the region 24.
As shown in FIG. 2, a spacer 25 is formed to isolate the semiconductor layer 16 in region 22 from the subsequently formed semiconductor layer 26. The semiconductor layer 26 is epitaxially grown in region 24, and thus has the same crystal orientation as the first semiconductor layer 12.
FIG. 3 illustrates the removal of the dielectric layer 18 and the formation of a shallow trench isolation (STI) region 27. The substrate 10 thus has two regions 16 and 26 that have different crystal orientations. Assuming the semiconductor layer 16 is in a (100) orientation and the semiconductor layer 26 is in a (110) orientation, an NFET 36 is then preferably formed on the semiconductor layer 16 and a PFET 38 is formed on the semiconductor layer 26, as illustrated in FIG. 4.
The crystal orientations of the semiconductor layers 16 and 26 are optimal for respective devices 36 and 38, and high performance can be achieved. However, the method suffers drawbacks. Trenches have to be formed in order to form STI regions that isolate devices 36 and 38. However, semiconductor layers 16 and 26 have different etching rates. This posts a challenge for the simultaneous etching process and subsequent chemical mechanical polish for planarizing surfaces. Additionally, the spacer 25 has to be formed to prevent epitaxial growth from the semiconductor layer 16. Since the spacer 25 has to have a minimum thickness so that it will not be completely etched during the cleaning processes, which are performed before growing the semiconductor layer 26, the scalability of the devices on the wafer is reduced.
What is needed, therefore, is a method of fabricating high performance MOSFETs on hybrid substrates with different crystal orientations, without the difficulty of forming STI regions in different regions having different characteristics. Additionally, scalability issues need to be resolved.